Clock devices

ABSTRACT

In a clock device wherein hours and minutes are displayed by a driving circuit including a &#39;&#39;&#39;&#39;second&#39;&#39;&#39;&#39; counter, a &#39;&#39;&#39;&#39;minute&#39;&#39;&#39;&#39; counter, and an &#39;&#39;&#39;&#39;hour&#39;&#39;&#39;&#39; counter, there is provided a correction key which provides a first signal for stopping the counting operation and clearing the content of the &#39;&#39;&#39;&#39;second&#39;&#39;&#39;&#39; counter and for stepping one step the content of the &#39;&#39;&#39;&#39;minute&#39;&#39;&#39;&#39; counter when the key is operated, and a second signal for causing the cleared &#39;&#39;&#39;&#39;second&#39;&#39;&#39;&#39; counter to commence the counting operation of seconds.

United States Patent 1191 Kashio June 18, 1974 [54] CLOCK DEVICES 3,668,859 6/1973 POllfl et a1 58/85.5 3,686,880 8/1972 Sa e'ima 58/23 R [75] Inventor T051 Kashm, Tokyo Japan 3,699,763 10/1972 26:11 58/50 R [73] Assignee: Casio Computer Co., Ltd., Tokyo,

Japan Primary Examiner-Richard B. Wilkinson p Assistant Examiner-U. Weldon Appl. No.2 350,201

Foreign Application Priority Data Apr. 13, 1972 Japan 47-37234 US. Cl. 58/85.5, 58/23 R References Cited UNITED STATES PATENTS 11/1970 Langley 58/50 R 4/1971 Walton 58/50 R Attorney, Agent, or Firm-Flynn & Frishauf ABSCT In a clock device wherein hours and minutes are displayed by a driving circuit including a second counter, a minute counter, and an hour" counter, there is provided a correction key which provides a first signal for stopping the counting operation and clearing the content of the second counter and for stepping one step the content of the minute counter when the key is operated, and a second signal for causing the cleared second counter to commence the counting operation of seconds.

8 Claims, 5 Drawing Figures COUNTER 16'- CLOCK PULSE GENERATOR PATENTEflJuu 18 1914 3.8171023 sum 1 OF 2 F G i F l G. 2

I l {2 F\ I l |3 --2? DRIVER 28W DRIVER OECOOER T 25 26M OECOOER 3 I COUNTER COUNTER COUNTER 3 I4 CORRECTION 19 y g KEY l o p/S IV 7 f ID COUNTER is CLOCK PULSE GENERATOR This invention relates to an improved electronic clock device which can effectively adjust or correct the time, particularly in a unit of seconds.

In the conventional clock device the time is displayed by means of a short hand which indicates hours and a long hand which indicates minutes. Thus, the time is analogously displayed by the rotation of the short and long hands on a dial plate, and the time adjustment is made by manually rotating the long hand. Thus, it is possible to adjust the time in a unit of seconds, for example 30 seconds or seconds by rotating the long hand to any desired positions on the dial plate.

In a recently developed digital clock wherein the time is displayed by digits, the digits utilized to display minutes are charged intermittently with a period of one minute. Accordingly, it is not possible to determine the instant at which the display of the minutes is stepped by merely watching the displayed digits so that adjustment of the minutes involves an error of a maximum of 1 minute. Thus it is difficult to accurately correct the time in the units of seconds.

Accordingly, it is an object of this invention to provide an improved clock device including simple means for accurately adjusting or correcting the time in a unit of seconds.

Another object of this invention is to provide a clock device including an improved electronic driving circuit of compact construction capable of providing digital or analogue display of hours and minutes even in clocks of small size and can accurately adjust or correct the displayed time in a unit of seconds.

SUMMARY OF THE INVENTION According to one aspect of this invention there is provided a clock device comprising a source of signals having a stable frequency, a second" counter to count signals from said signal source and for generating 1 minute stepping signals at a rate of one per 60 seconds, a minute counter to count the one minute stepping signals for generating one hour stepping signals at a rate of one per 60 minutes, an .hour" counter for counting the 1 hour stepping signals, and means to generate a first signal for stopping the counting operation and clearing the content of the second counter and for stepping by one step the content of the min- 'ute" counter and a second signal for causing the cleared second counter to commence the counting operation of seconds from the initial count thereof. A pulse signal for stepping by one the contents of a counting circuit is hereinafter referred to as a stepping signal."

According to another aspect of this invention there is provided a clock device comprising a source of signals having a stable frequency a second counter to count signals from said signal source and for generating l minute stepping signals at a rate of one per 60 seconds, a minute counter to count the 1 minute stepping signals for generating 1 hour stepping signals at I a rate of one per 60 minutes, an hour counter for counting 1 hour" stepping signals, and means to generate a first signal for stopping the counting operation and clearing the content of the second counter and to generate a second signal for causing the cleared second counter to commence the counting operation of signals from the initial count thereof and advancing by one step the content of the minute counter.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. I is a plan view of a digital wrist watch embodying the invention;

FIG. 2 is a block diagram showing the driving and control circuit for the watch shown in FIG. 1;

FIG. 3 shows one example of a circuit which generates a minute stepping signal when the correction key shown in FIG. 2 is operated;

FIG. 4 shows one example of a circuit which generates a minute stepping signal when the correction key shown in FIG. 2 is released; and

FIG. 5 is a block diagram showing another example of time correcting controller.

DETAILED DESCRIPTION OF ILLUSTRATED EMBODIMENTS In the following, a preferred embodiment of this invention as applied to a digital wrist watch will be described. A display plate 11a of a body 11 of a digital wrist watch shown in FIG. 1 is provided with an hour display section 12 and a minute display section 13, each consisting of two digits. These hour" and minute display sections 12 and 13 are made up of a plurality of liquid crystal display elements or digit display tubes so as to display any time, for example 10 oclock and 29 minutes. A time adjusting or correction key 14 is provided on the display plate 11a and the body 11 is secured to a wrist of a user by means of a band 15.

Referring now to FIG. 2, clock signals utilized as the reference for counting the time are generated by a clock pulse generator 16 and are sent to an n-step counter 18 through one input of an AND gate circuit 17. Since the output of key 14 (which is coupled, for example, to a voltage source V) is applied to the other input of AND gate circuit 17 through an inverter 19, when the key 14 is not operated or released the clock pulses are continuously supplied to the counter 18. When the number of the steps n of the counter 18 and the frequency F of the clock pulse are set to satisfy a relation 1/n F 1, then the counter 18 will produce one carry signal at each second. The counter 18 is reset by the output of key 14. The carry signal or second signal generated by counter 18 is applied to the inputs of an AND gate circuit 20 together with the output from inverter 19 and the output from AND gate circuit 20 is applied as the second signal to a second counting circuit in the form of a 60-step counter 21. The counter 21 is constructed to be reset by the output from key 14 and the carry signal generated by this counter is applied to a 60-step minute counter 23 through an OR gate circuit 22 together with the output from key 14. The carry signal generated by counter 23 is applied to a l2-step hour counter 24.

The contents of minute counter 23 and hour counter 24 are supplied to decoders 25 and 26, respectively, where they are converted into signals suitable for use in the display elements utilized in minute and hour display sections 13 and 12. The outputs from decoders 25 and 26 are impressed upon minute and hour display sections 13 and 12 via drivers 27 and 28, respectively, to drive these sections to provide a visible display of the time, for example, 10 oclock 29 minutes. 1

,The clock device operates as follows. Under the nor- 7 mal condition where the correction key or button 14 is not operated, the AND gate circuit 17 is enabled to cause counter 18 to count the number of pulses generated by the clock pulse generator 16 so as to provide carry signals to counter 21 through enabled AND gate circuit 20 at a rate of one carry signal per second. The carry signals generated by counter 21 are supplied to counter 23 at a rate of one per minute. The carry signals produced by counter 23 are hour stepping sig nals produced at a rate of one per hour so that the content of counter 24 represents hours. Consequently, when the key 14 is not operated, hour and minute display sections 12 and 13 of the'watch 11 provides a digital display of hours and minutes corresponding to the contents of counters-24 and 23, respectively.

Where it is desired to correct the display of the time, the correction key 14 is operated. The resulting signal not only resets counter 18 but also clears counter 21.

At the same time, this signal is also applied to counter 23 as the minute stepping signal. Under these conditions, gate signals of AND gate circuits 17 and 20 are interrupted so that the counting operation of the counter 18 is stopped and the input to second counter 21 is also interrupted. The operation of the correction key 14 is continued until the time'that has been displayed by the minutes display section 13 is reached. For example, when correction key 14 is operated at a time of oclock 29 minutes as shown in FIG. 1 the time display will be changed to 10 oclock 30 minutes and the key 14 is released when the standard time reaches 10 oclock 30 minutes. As a result, the clock pulses are applied to counter 18 to commence its counting operation at an instant when the standard time reaches 10 oclock 30 minutes. Thus, the time display of the watch is matched with the standard time at an instant of IO oclock, 30 minutes and zero seconds. In this manner, the minute display is advanced one step by the operation of the correction key .14 whereas the counting operation of the clock pulses is commenced in response to the release of the correction key 14, so that it is possible to correct ormatch the time displayed in a unit of seconds at high accuracies by taking the commencement of the minute display as the reference.-

FIG. 3 shows one example of a signal generating circuit which is used in combination with correction key 14 for supplying a stepping signal to the minute counter 23 when key 14 is operated. The signal generating circuit comprises a delay circuit 31 for delaying the signal from key 14' by a predetermined interval, an inverter 32 to which the output of the delay circuit 31 is applied, and an AND gate circuit 33 supplied with the outputs from inverter 32 and key 14. If the key 14 is not operared, a 1 output signal from inverter 32 is applied to one input of the AND gate circuit 33 and a 0 signal is applied to theother input, so the AND gate circuit 33 will produce a 0 output. Upon operation of key 14, the input signal to the other input of the AND gate circuit 33 will be changed to l with the result that the 1 output is applied to counter 23 as a minute stepping signal. As a predetermined interval elapses after the instant when the outputf AND gate circuit 33 has been changed to 1, the inverter 32 provides a 0 output in response to the 1 output from delay circuit 31, thus completing the operation resulting from the operation of the correction key 14. The

circuit shown in FIG. 3 may be interposed between a juncture 29 and one input of the OR gate circuit 22.

As above described, although the circuit shown in FIG. 3 is constructed such that a minute stepping signal is applied to counter 23 whenever the key 14 is operated, it is also possible to construct the signal generating circuit such that it provides a minute stepping signal to counter 23 whenever the key 14 is released. FIG. 4 shows one example of such modified circuit which can also be used in combination with the circuit shown in FIG. 2. In the circuit shown in FIG. 4, the output from key 14 is applied to one input of an AND gate circuit 35 through a delay circuit 34 while at the same time to the other input of the AND gate circuit 35 via an inverter 36.

Upon operation of key 14 as the input to inverter 36 is a 1, the one input to the AND gate circuit 35 is a 0 so that no signal is applied to counter 23. Under these conditions, when key 14 is released, AND gate circuit 35 provides a 1 output because at this time the output from delay circuit 34 is still a 1 signal, and the 1 output from the AND gate circuit 35 is applied to counter 23 as a minute stepping signal. As a predetermined interval elapses under these conditions, the output of delay circuit 34 will be changed to a 0, thus disenabling AND gate circuit 35. I

Inasmuch as the circuit shown in FIG. 2 is constructed such that the minute counter 23 is steppedup'one count by the operation of key in, a maximum of one minute is often required between the operation and the release of the key 14. FIG. 5 shows an improved circuit which can obviate this inconvenience, that can reduce the time required for correcting the time display occurring as a result of the operation of key 14 to less than 10 seconds. In the modification shown'in FIG. 5, counter 21 shown in FIG. 2 is replaced by two counters 40 and 41, and an OR gate circuit 42. More specifically, the output from key 14 is applied to one input of AND gate circuit 20 to apply second signals to one input of a lO-step counter 40 at a rate of one per second. Counter 40 operates to apply carry signals to a sixstep counter 41 through an OR gate circuit 42 at a rate of one signal per 10 seconds, and the counter 41 operates to send carry signals to counter 23 at a rate of one signal per minute. The signal from key 14 is also applied to counter 40 as a clear signal and to counter 41 as a stepping signal.

Thus, whenever the key 14 is operated, AND gate circuit 20 is disabled-to terminate the counting operation of counter40 while at the same time its content is cleared to supply a stepping signal to counter 41. Like the embodiment shown in FIG. 2, in the modified embodiment shown in FIG. 5 too, by releasing key 14 at an instant when the time counted by counter 41 matches with the standard time, it would be possible to reduce the interval between the operation and release of the correction key 14 to a maximum of 10 seconds.

In the foregoing embodiments the circuits were constructed such that when the correction key is operated,

' the second counter was cleared and counters of keys, the first one being used to set a memory device, for example, a flip-flop circuit, to memorize the operation of the first key and the second key being used to reset the memory device. Alternatively, a single key may be combined with a flip-flop circuit such that when the key is operated the flip-flop circuit is set, that when the key is released the flip-flop circuit is reset and that the flip-flop circuit produces orders for operating and releasing the key.

It will be clear that the invention can also be applied to analogue display clocks. Thus, for example, when the electronic driving and counting circuits are incorporated into an analogue display clock the outputs from drivers may be supplied to 60 minute" display elements and 12 hour display elements which are arranged on circles on the dial plate of a watch.

What is claimed is:

l. A clock device comprising:

a source of signals having a stable frequency;

a second counter to count signals from said signal source and for generating 1 minute stepping sig nals at a rate of one per 60 seconds;

a minute counter to count said 1 minute stepping signals and for generating 1 hour stepping signals at a rate of one per 60 minutes;

an hour counter for counting said 1 hour counting signals; and

means coupled to said signal source, said second counter, and said minute counter for generating a first signal for stopping the counting operation and clearing the content of said second counter and for stepping by one step the content of said minute counter and for generating a second signal for causing said cleared second counter to commence a counting operation of signals from the initial count thereof.

2. A clock device according to claim 1 wherein said means for generating said first and second signals comprises a time correction key, said first signal being generated when said key is operated and said second signal being generated when said key is released.

3. A clock device comprising:

a source of signals having a stable frequency;

a second counter to count signals from said signal source and for generating 1 minute stepping signals at a rate of one per 60 seconds;

a minute counter to count said 1 minute stepping signals for generating 1 hour stepping signals at a rate of one per 60 minutes;

an hour counter for counting said 1 hour stepping signals; and

means coupled to said signal source, said second counter, and said minute counter for generating a first signal for stopping the counting operation and clearing the content of said second counter and for generating a second signal for causing said cleared second counter to commence the counting operation of signals from the initial count thereof and advancing by one step the content of said minute counter.

4. A clock device according to claim 3 wherein said means for generating said first and second signals comprises a time correction key, said first signal being generated when said key is operated and said second signal being generated when said key is released.

5. A clock device according to claim 1 wherein said source of signals comprises a clock signal generating circuit for generating a standard high frequency signal; and a frequency dividing counter for reducing the frequency of said standard high frequency signal, said reduced frequency signal being counted by said second counter.

6. A clock device according to claim 1 wherein said first signal is coupled to said frequency dividing counter for resetting said frequency dividing counter.

counter for resetting said frequency dividing counter. 

1. A clock device comprising: a source of signals having a stable frequency; a ''''second'''' counter to count signals from said signal source and for generating ''''1 minute'''' stepping signals at a rate of one per 60 seconds; a ''''minute'''' counter to count said ''''1 minute'''' stepping signals and for generating ''''1 hour'''' stepping signals at a rate of one per 60 minutes; an ''''hour'''' counter for counting said ''''1 hour'''' counting signals; and means coupled to said signal source, said ''''second'''' counter, and said ''''minute'''' counter for generating a first signal for stopping the counting operation and clearing the content of said ''''second'''' counter and for stepping by one step the content of said ''''minute'''' counter and for generating a second signal for causing said cleared ''''second'''' counter to commence a counting operation of signals from the initial count thereof.
 2. A clock device according to claim 1 wherein said means for generating said first and second signals comprises a time correction key, said first signal being generated when said key is operated and said second signal being generated when said key is released.
 3. A clock device comprising: a source of signals having a stable frequency; a ''''second'''' counter to count signals from said signal source and for generating ''''1 minute'''' stepping signals at a rate of one per 60 seconds; a ''''minute'''' counter to count said ''''1 minute'''' stepping signals for generating ''''1 hour'''' stepping signals at a rate of one per 60 minutes; an ''''hour'''' counter for counting said ''''1 hour'''' stepping signals; and means coupled to said signal source, said ''''second'''' counter, and said ''''minute'''' counter for generating a first signal for stopping the counting operation and clearing the content of said ''''second'''' counter and for generating a second signal for causing said cleared ''''second'''' counter to commence the counting operation of signals from the initial count thereof and advancing by one step the content of said ''''minute'''' counter.
 4. A clock device according to claim 3 wherein said means for generating said first and second signals comprises a time correction key, said first signal being generated when said key is operated and said second signal being generated when said key is released.
 5. A clock device according to claim 1 wherein said source of signals comprises a clock signal generating circuit for generating a standard high frequency signal; and a frequency dividing counter for reducing the frequency of said standard high frequency signal, said reduced frequency signal being counted by said ''''second'''' counter.
 6. A clock device according to claim 1 wherein said first signal is coupled to said frequency dividing counter for resetting said frequency dividing counter.
 7. A clock device according to claim 3 wherein said source of signals comprises a clock signal generating circuit for generating a standard high frequency signal; and a frequency dividing counter for reducing the frequency of said standard high frequency signal, said reduced frequency signal being counted by said ''''second'''' counter.
 8. A clock device according to claim 3 wherein said first signal is coupled to said frequency dividing counter for resetting said frequency dividing counter. 